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HM5116100 series 16 m fp dram (16-mword 1-bit) 4 k refresh ade-203-646e (z) rev. 5.0 nov. 1997 description the hitachi HM5116100 is a cmos dynamic ram organized 16,777,216-word 1-bit. it employs the most advanced 0.5 m m cmos technology for high performance and low power. the HM5116100 offers fast page mode as a high speed access mode. it is packaged in 26-pin plastic soj. features single 5 v ( 10%) access time: 60 ns/70 ns (max) power dissipation ? active mode: 440 mw/385 mw (max) ? standby mode 11 mw (max) fast page mode capability refresh cycles ? 4096 refresh cycles : 64 ms 3 variations of refresh ? ras -only refresh ? cas -before- ras refresh ? hidden refresh test function ? 16-bit parallel test mode ordering information type no. access time package HM5116100s-6 HM5116100s-7 60 ns 70 ns 300-mil 26-pin plastic soj (cp-26/24db)
HM5116100 series 2 pin arrangement 26 25 24 23 22 21 19 18 17 16 15 14 1 2 3 4 5 6 8 9 10 11 12 13 v cc din nc we ras a11 a10 a0 a1 a2 a3 v cc v dout nc cas nc a9 a8 a7 a6 a5 a4 v ss ss HM5116100s series (top view) pin description pin name function a0 to a11 address input row/refresh a0 to a11 column a0 to a11 din data input dout data output ras row address strobe cas column address strobe we read/write enable v cc power supply v ss ground nc no connection
HM5116100 series 3 block diagram timing and control column address buffers row address buffers ? ? ? ? ? ? a0 a1 to a11 ras cas we column decoder row decoder 16m array din dout din buffer dout buffer
HM5116100 series 4 absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v t C1.0 to +7.0 v supply voltage relative to v ss v cc C1.0 to +7.0 v short circuit output current iout 50 ma power dissipation p t 1.0 w operating temperature topr 0 to +70 c storage temperature tstg C55 to +125 c recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit note supply voltage v cc 4.5 5.0 5.5 v 1 input high voltage v ih 2.4 6.5 v 1 input low voltage v il C1.0 0.8 v 1 note: 1. all voltage referred to v ss
HM5116100 series 5 dc characteristics (ta = 0 to +70 c, v cc = 5 v 10%, v ss = 0 v) HM5116100 -6 -7 parameter symbol min max min max unit test conditions operating current *1, *2 i cc1 80 70 ma t rc = min standby current i cc2 2 2 ma ttl interface ras , cas = v ih dout = high-z 1 1 ma cmos interface ras , cas 3 v cc C 0.2v dout = high-z ras -only refresh current *2 i cc3 80 70 ma t rc = min standby current *1 i cc5 5 5 ma ras = v ih , cas = v il dout = enable cas -before- ras refresh current i cc6 80 70 ma t rc = min fast page mode current *1, *3 i cc7 70 60 ma t pc = min input leakage current i li C10 10 C10 10 m a 0 v vin 7 v output leakage current i lo C10 10 C10 10 m a 0 v vout 7 v dout = disable output high voltage v oh 2.4 v cc 2.4 v cc v high iout = C5 ma output low voltage v ol 0 0.4 0 0.4 v low iout = 4.2 ma notes: 1. i cc depends on output load condition when the device is selected. i cc max is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. address can be changed once or less while cas = v ih . capacitance (ta = 25 c, v cc = 5 v 10%) parameter symbol typ max unit notes input capacitance (address, data-in) c i1 5 pf 1 input capacitance (clocks) c i2 7 pf 1 output capacitance (data-out) c o 7 pf 1, 2 notes: 1. capacitance measured with booton meter or effective capacitance measuring method. 2. cas = v ih to disable dout.
HM5116100 series 6 ac characteristics (ta = 0 to +70 c, v cc = 5 v 10%, v ss = 0 v) *1, *2, *16 test conditions input rise and fall time : 5 ns input timing reference levels : 0.8 v, 2.4 v output load : 2 ttl gate + c l (100 pf) (including scope and jig) read, write, read-modify-write and refresh cycles (common parameters) HM5116100 -6 -7 parameter symbol min max min max unit notes random read or write cycle time t rc 110 130 ns ras precharge time t rp 40 50 ns cas precharge time t cp 10 10 ns ras pulse width t ras 60 10000 70 10000 ns cas pulse width t cas 15 10000 18 10000 ns row address setup time t asr 00ns row address hold time t rah 10 10 ns column address setup time t asc 00ns column address hold time t cah 10 15 ns ras to cas delay time t rcd 20 45 20 52 ns 3 ras to column address delay time t rad 15 30 15 35 ns 4 ras hold time t rsh 15 18 ns cas hold time t csh 60 70 ns cas to ras precharge time t crp 55ns transition time (rise and fall) t t 3 50 3 50 ns 5
HM5116100 series 7 read cycle HM5116100 -6 -7 parameter symbol min max min max unit notes access time from ras t rac 60 70 ns 6, 7, 17 access time from cas t cac 15 18 ns 7, 8, 15, 17 access time from address t aa 30 35 ns 7, 9, 15, 17 read command setup time t rcs 00ns read command hold time to cas t rch 00ns10 read command hold time to ras t rrh 00ns10 column address to ras lead time t ral 30 35 ns column address to cas lead time t cal 30 35 ns cas to output in low-z t clz 00ns output data hold time t oh 33ns output buffer turn-off time t off 15 15 ns 11 write cycle HM5116100 -6 -7 parameter symbol min max min max unit notes write command setup time t wcs 00ns12 write command hold time t wch 10 15 ns write command pulse width t wp 10 10 ns write command to ras lead time t rwl 15 18 ns write command to cas lead time t cwl 15 18 ns data-in setup time t ds 00ns13 data-in hold time t dh 10 15 ns 13
HM5116100 series 8 read-modify-write cycle HM5116100 -6 -7 parameter symbol min max min max unit notes read-modify-write cycle time t rwc 130 153 ns ras to we delay time t rwd 60 70 ns 12 cas to we delay time t cwd 15 18 ns 12 column address to we delay time t awd 30 35 ns 12 refresh cycle HM5116100 -6 -7 parameter symbol min max min max unit notes cas setup time (cbr refresh cycle) t csr 55ns cas hold time (cbr refresh cycle) t chr 10 10 ns we setup time (cbr refresh cycle) t wrp 00ns we hold time (cbr refresh cycle) t wrh 10 10 ns ras precharge to cas hold time t rpc 55ns fast page mode cycle HM5116100 -6 -7 parameter symbol min max min max unit notes fast page mode cycle time t pc 40 45 ns fast page mode ras pulse width t rasp 100000 100000 ns 14 access time from cas precharge t cpa 35 40 ns 7, 15, 17 ras hold time from cas precharge t cprh 35 40 ns
HM5116100 series 9 fast page mode read-modify-write cycle HM5116100 -6 -7 parameter symbol min max min max unit notes fast page mode read-modify-write cycle time t prwc 60 68 ns we delay time from cas precharge t cpw 35 40 ns 12 test mode cycle * 16 HM5116100 -6 -7 parameter symbol min max min max unit notes test mode we setup time t wts 00ns test mode we hold time t wth 10 10 ns refresh cycle parameter symbol max unit note refresh period t ref 64 ms 4096 cycles
HM5116100 series 10 notes: 1. ac measurements assume t t = 5 ns. 2. an initial pause of 200 m s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing ras -only refresh or cas -before- ras refresh). if the internal refresh counter is used, a minimum of eight cas -before- ras refresh cycles are required. 3. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 4. operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 5. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih (min) and v il (max). 6. assume that t rcd t rcd (max) and t rad t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 7. measured with a load circuit equivalent to 2 ttl loads and 100 pf. 8. assume that t rcd 3 t rcd (max) and t rad t rad (max). 9. assume that t rcd t rcd (max) and t rad 3 t rad (max). 10. either t rch or t rrh must be satisfied for a read cycles. 11. t off (max) and t oez (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 12. t wcs , t rwd , t cwd , t awd and t cpw are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only; if t wcs 3 t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t rwd 3 t rwd (min), t cwd 3 t cwd (min), and t awd 3 t awd (min), or t cwd 3 t cwd (min), t awd 3 t awd (min) and t cpw 3 t cpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 13. these parameters are referenced to cas leading edge in early write cycles and to we leading edge in delayed write or read-modify-write cycles. 14. t rasp defines ras pulse width in fast page mode cycles. 15. access time is determined by the longest among t aa , t cac and t cpa . 16. the 16m dram offers a 16-bit time saving parallel test mode. address ca0, ca1, ca10 and ca11 for the 16m 1 are dont care during test mode. test mode is set by performing a we - and- cas -before- ras (wcbr) cycle. in 16-bit parallel test mode, data is written into 16 bits in parallel at din and read out from dout. if 16 bits are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then the device has passed. if they are not equal, data output pin is a low state, then the device has failed. refresh during test mode operation can be performed by normal read cycles or by wcbr refresh cycles. to get out of test mode and enter a normal operation mode, perform either a regular cas - before- ras refresh cycle or ras -only refresh cycle. 17. in a test mode read cycle, the value of t rac , t aa , t cac and t cpa is delayed by 2 ns to 5 ns for the specified value. these parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 18. xxx: h or l (h: v ih (min) v in v ih (max), l: v il (min) v in v il (max)) ///////: invalid dout
HM5116100 series 11 timing waveforms *18 read cycle ras cas address we dout t ras t rc t rp t csh t rcd t rsh t cas t ral t cal t cah t rad t t asr rah t asc t rcs t rch t rrh t oh t cac t off t aa t rac t clz t t t crp row column dout
HM5116100 series 12 early write cycle ras address we din dout t rc * t ras t rp t crp t csh t rcd t rsh t cas t t t asr t rah t asc t cah column row t wcs t wch t ds t dh din t wcs wcs (min) high-z* t cas
HM5116100 series 13 delayed write cycle address cas ras we din dout t ras t rc t rp t csh t crp t rcd t rsh t cas t asr t rah t asc t cah row column t rcs t wp t rwl t cwl t ds t dh din invalid dout t clz t off t t
HM5116100 series 14 read-modify-write cycle din dout we address cas ras t ras t rwc t rp t crp t t t rcd t cas t rad t asr t rah t cah t asc row column t cwd t rcs t awd t rwd t wp t cwl t rwl t ds t dh din dout t cac t aa t oh t off t rac t clz
HM5116100 series 15 ras -only refresh cycle ras cas address dout high-z row t rc t rp t ras t t t crp t rpc t crp t asr t rah t off cas -before- ras refresh cycle ras cas we address dout high-z t off t wrp t wrh t wrp t wrh t cp t rpc t csr t chr t cp t rpc t csr t chr t crp t rp t ras t rc t rc t rp t ras t rp t t
HM5116100 series 16 hidden refresh cycle address we dout cas ras t rc t rc t rc t rp t ras t rp t ras t rp t ras t t t rsh t chr t crp t rcd t rad t ral t cah t asc t rah t asr row column t rcs t cac t aa t rac t clz dout t oh t off t rrh t wrp t wrh t wrp t wrh
HM5116100 series 17 fast page mode read cycle address we dout cas ras t rasp t cprh t rp t t t csh t pc t rsh t rcd t cas t cp t cas t cp t cas t crp t rad t cal t cal t cal t ral t asr t rah t cah t cah t cah t asc t asc row column 1 column 2 column n t rch t rrh t rcs t rch t rch t rcs t rcs t cac t aa t rac t cpa t cpa t aa t aa t clz dout 1 dout 2 dout n t oh t off t cac t clz t oh t off t cac t clz t oh t off t asc
HM5116100 series 18 fast page mode early write cycle * t wcs wcs (min) ras cas address we din dout t rasp t rp t t t csh t pc t rsh t crp t cas t cp t cas t cp t cas t rcd t asr t rah t asc t cah t asc t cah t asc t cah t wch t wcs t wch t wcs t wch t wcs t dh t ds t dh t ds t dh t ds din 1 din 2 din n high-z* t row column 1 column 2 column n
HM5116100 series 19 fast page mode delayed write cycle din we address ras dout cas t rasp t rp t t t csh t pc t rsh t cas t rcd t cp t cas t cp t cas t crp t asr t rah t asc t cah t asc t cah t asc t cah row column 1 column 2 column n t wp t rcs t rcs t wp t rcs t wp t rwl t cwl t cwl t cwl t ds t dh t ds t dh t ds t dh din 1 din 2 din n t clz t off t clz t off t clz t off invalid dout invalid dout invalid dout
HM5116100 series 20 fast page mode read-modify-write cycle dout din we address cas ras t rasp t rp t t t prwc t rcd t cas t cp t cas t cp t cas t crp t rad t cah t cah t cah t asr t rah t asc t asc t asc row column 1 column 2 column n t rcs t rwd t awd t awd t rcs t rcs t rwl t cwl t cwl t cwl t awd t wp t wp t wp t cwd t cpw t cwd t cwd t cpw t ds t ds t ds t dh t dh t dh din 1 din 2 din n t cac t cac t cac t aa t cpa t cpa t rac t oh t aa t aa t oh t oh t off t clz t off t clz t clz t off dout 1 dout 2 dout n t rsh
HM5116100 series 21 test mode cycle * 16 cbr or ras -only refresh ras cas we set cycle** test mode cycle *,** reset cycle normal mode ** * address, din: h or l test mode set cycle @ @@ ? ?? @ @@ ? ?? @ @@ ? ?? @ @@ ? ?? @ @@ ? ?? cas we address dout ras t rc t rp t ras t rp t chr t csr t rpc t rpc t crp t t t cp t wts t wth t cp t off high-z
HM5116100 series 22 package dimensions HM5116100s series (cp-26/24db) 16.90 17.27 max 0.74 7.62 0.13 8.51 0.13 26 14 113 0.10 0.43 0.10 3.50 0.26 19 21 8 6 2.65 0.12 1.30 max 0.80 +0.25 ?.17 2.54 1.27 hitachi code jedec eiaj weight (reference value) cp-26/24db conforms conforms 0.8 g 0.41 0.08 unit: mm dimension including the plating thickness base material dimension 6.79 + 0.19 ?0.18
HM5116100 series 23 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi semiconductor (america) inc. 2000 sierra point parkway brisbane, ca. 94005-1897 u s a tel: 800-285-1601 fax:303-297-0447 hitachi europe gmbh continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30-00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 01628-585000 fax: 01628-585160 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071 copyright ?hitachi, ltd., 1997. all rights reserved. printed in japan.
HM5116100 series 24 revision record rev. date contents of modification drawn by approved by 1.0 oct. 14, 1996 initial issue y. kasama m. mishima 2.0 dec. 10, 1996 addition of HM5116100-5 series y. kasama y. matsuno 3.0 feb. 27, 1997 ac characteristics t rrh min: 5/5/5 ns to 0/0/0 ns y. kasama y. matsuno 4.0 jun. 24, 1997 deletion of HM5116100-5 series y. kasama y. matsuno 5.0 nov. 1997 change of subtitle

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